ADC circuits are useful in many applications where it may be desirable to quantize an analog input signal into a digital output signal. A variety of ADC architectures have been employed in conventional architectures including flash converters, folding converters, sub-ranging converters, multi-step converters, pipeline converters and successive approximation converters.
Flash converters are typically faster than other types of conventional ADC circuits such as successive approximation converters. However, a high precision flash converter may require a huge number of comparators compared to other ADCs, especially as the precision increases. For example, a typical n-bit flash converter may require 2n−1 comparators. The size and cost of the numerous comparators may be impracticable for many applications (e.g., an 8-bit converter can require more than 255 comparators). In place of the comparators, many other high speed ADC circuits (e.g., pipeline and folding converters) substitute more complex architectures requiring fewer comparators.
A folding ADC is similar in basic architecture to a flash converter, where the overall number of comparators is reduced by adding a folding circuit to the front end of the conversion. Instead of using the comparators to distinguish just one code transition as in a typical flash converter, a folding ADC converter re-uses the existing comparators multiple times. If an m times folding circuit is used in an n-bit ADC, the actual number of comparator can be reduced from 2n−1, to 2n/m, where m is the number of folded regions for the folding operation. Typical folding circuits can also be referred to as Gilbert multiplier circuits or analog wired-OR circuits.
An example folding ADC is illustrated in FIG. 1A. The folding ADC includes a reference circuit, an array (1-N) of cascaded folding amplifier stages, an array of fine-resolution comparator circuits, one or more coarse amplifier circuits, one or more coarse comparator circuits, and an encoder circuit. An input signal (VIN) is applied to the input of the cascaded folding amplifier stages, and also to the coarse amplifier circuits. The reference circuit is arranged to provide reference levels to the first stage of the cascaded folding amplifier circuits, and also to the first stage of the coarse amplifier circuits. Optionally, a track and hold circuit can be used to supply the input signals to the amplifiers. In addition, an optional first stage (STAGE 0) can be used to combine the input signal with the reference voltages and provide voltage amplification. The outputs of the cascaded folding amplifier stages are applied to an input of the fine comparator circuits. The outputs of the coarse amplifier circuits are applied to an input of the coarse comparator circuits. The output of the fine and coarse comparator circuits are evaluated by the encoder, which in turn generates a group of least significant bits (LSB Bits) and most significant bits (MSB bits), which corresponds to the output of the converter. The folding converter determines the LSB Bits through the use of analog preprocessing with a folding converter topology including the cascaded folding amplifier stages and the fine comparators. The MSB Bits are determined by a coarse converter topology including the coarse amplifiers and the coarse comparators. An additional synchronization bit can be used to make sure that the MSB and LSB evaluation is done consistently, especially when the input signal is at the boundary of a MSB code transition.
In an example 5-bit folding ADC, 10 comparators can be used as the fine and coarse converter circuits. For example, as illustrated in FIG. 1B, MSB Bits are found by comparing the input signal (VIN) to three different thresholds (e.g., VFSx ¼, ½ and ¾) as a percentage of the full scale voltage (VFS) to provide a two-bit output by decoding the output from three comparators. As illustrated in FIG. 1C, LSB Bits can be found by cyclically (through the folding amplifier) comparing the input signal (YIN) to seven thresholds (e.g., VFSx 1/7, 2/7 . . . 1). between as a percentage of the full scale voltage (VFS) to provide a three-bit output from seven comparators.